These shift registers consist of five R-S master-slave flip-flops connected to perform parallel to serial or serial to parallel conversion of binary data. Since both inputs and outputs for all flip-flops are accessible, parallel.in/parallel out or serial-in/serial-out operation may be performed. All flip flops are simultaneously set to a low Output level by applying a low level voltage to the clear input while the preset is inactive (low). Clearing is independent of the level of the clock input.
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